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Semiconductor
T nt DUC PRO placeme LETE Re BSO mended O October 1998 com o Re N
HFA5253
File Number 4003.4
800MHz, Ultra High-Speed Monolithic Pin Driver
The HFA5253 is a very high speed monolithic pin driver solution for high performance test systems. The device will switch at high data rates between two input voltage levels providing variable amplitude pulses. Slew Rate Control pins provide independent control over positive and negative slew rate allowing the customer to optimize the pin driver speed for their application. The output impedance is trimmed to achieve a precision 50 source for impedance matching. Two differential ECL/TTL compatible inputs control the operation of the HFA5253, one controlling the VHIGH/VLOW switching and the other controlling the output's highimpedance state. The HFA5253's 800MHz data rate makes it compatible with today's high-speed VLSI test systems and the +8V to -3V output swing satisfies the most stringent testing requirements of all common logic families. The HFA5253 is manufactured in Harris' proprietary complementary bipolar UHF-1 process.
Features
* High Digital Data Rate . . . . . . . . . . . . . . . . . . . . . 800MHz * Very Fast Rise/Fall Times. . . . . . . . . . . . . . . . . . . . . 500ps * Wide Output Range . . . . . . . . . . . . . . . . . . . . . +8V to -3V * Precise 50 Output Impedance * High Impedance, Three-State Output Control * Slew Rate Control
Applications
* IC Tester Pin Electronics * Pattern Generators * Pulse Generators * Level Comparator/Translator
Part Number Information
PART NUMBER HFA5253CB TEMP. RANGE (oC) 0 to 50 PACKAGE 20 Ld PSOP PKG. NO. M20.3A
Pinout
HFA5253 (PSOP) TOP VIEW
Block Diagram
INPUT BUFFER VHIGH VCC1 VCC1 VCC2 VCC2 VOUT NC VEE2 VEE2 VEE1 1 2 3 4 5 6 7 8 9 20 VHIGH 19 +SRC 18 NC 17 DATA 16 DATA 15 NC 14 HIZ 13 HIZ 12 -SRC 11 VLOW -SRC VLOW INPUT BUFFER HIZ HIZ + DATA DATA + Q Q +SRC
-
VCC 50 VOUT
-
VEE
VEE1 10
POWER PSOP PACKAGE (HEAT SLUG SURFACE IS ELECTRICALLY FLOATING)
TRUTH TABLE FOR VOUT DATA 0 0 HIZ 1 VLOW HIZ 1 VHIGH HIZ
89
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1998
HFA5253 Pin Descriptions
NAME VCC1 FUNCTION Positive Supply. Nominal value is 11.2V 0.2V. Reducing supply voltage below 11.0V will reduce positive output voltage swing. The total supply voltage from VCC1 to VEE1 should not exceed 18.0V for normal operation or exceed 19.0V to prevent damage. Harris recommends two wire bonds to this pad to provide the lowest possible impedance. In addition, power supply decoupling chip capacitors of 470pF, 0.1F and a 10F tantalum are recommended. Do not connect the VCC1 and VCC2 pins together immediately, rather run separate traces until they can be joined at a large bypass capacitor (0.1F || 10.0F). Negative Supply. Nominal value is -6.4V 0.2V. A supply voltage more positive than -6.2V will reduce negative output voltage swing. The total supply voltage from VCC1 to VEE1 should not exceed 18.0V for normal operation or exceed 19.0V to prevent damage. Harris recommends two wire bonds to this pad to provide the lowest possible impedance. In addition, power supply decoupling chip capacitors of 470pF, 0.1F and a 10F tantalum are recommended. Do not connect the VEE1 and VEE2 pins together immediately, rather run separate traces until they can be joined at a large bypass capacitor (0.1F || 10.0F). Output Stage Positive Supply. Nominal voltage and cautions are the same as for VCC1. Having decoupling chip capacitors close to VCC2 and VEE2 is essential since large AC current will flow through this pad to the output during transients. Harris recommends two wire bonds for this pad. Do not connect the VCC1 and VCC2 pins together immediately, rather run separate traces until they can be joined at a large bypass capacitor (0.1F || 10.0F). Output Stage Negative Supply. Nominal voltage and cautions are the same as for VEE1. Having decoupling chip capacitors close to VCC2 and VEE2 is essential since large AC current will flow through this pad to the output during transients. Harris recommends two wire bonds for this pad. Do not connect the VEE1 and VEE2 pins together immediately, rather run separate traces until they can be joined at a large bypass capacitor (0.1F || 10.0F). Input Voltage High is used to set the output high level VOH. VHIGH is sensitive to capacitively coupled AC noise. Protection from high frequency noise can be achieved with a low pass filter consisting of a 50 chip resistor and a 470pF chip capacitor. Without this precaution the pin driver may oscillate due to feedback from the output through the PC board ground. Input Voltage Low is used to set the output low level VOL. VLOW is sensitive to capacitively coupled AC noise. Protection from high frequency noise can be achieved with a low pass filter consisting of a 50 chip resistor and a 470pF chip capacitor. Without this precaution the pin driver may oscillate due to feedback from the output through the PC board ground. Driver Output. The output impedance has been laser trimmed to match a 50 transmission line 2. Custom output impedance trimming is available (contact sales office for details) to provide the best match possible to your 50 system. Differential Digital Inputs used to switch VOUT to the VHIGH or VLOW level. Harris recommends this input pair be driven by complementary ECL signals to provide optimal switching speeds and timing accuracy. However a large Common Mode and Differential Voltage Range is provided to accommodate a variety of signals including single ended TTL and CMOS. When using single ended signals the other input must be tied to an appropriate threshold voltage. Differential Digital Inputs used to switch VOUT from an Active to a High Impedance State. Harris recommends that this input pair be driven by complementary ECL signals to provide optimal switching speeds and timing accuracy. However a large Common Mode and Differential Voltage Range is provided to accommodate a variety of signals including single ended TTL and CMOS. When using single ended signals the other input must be tied to an appropriate threshold voltage. The Positive Slew Rate Control Pin adjusts the rising edge slew rate with an external current ISTEAL. ISTEAL draws current (0mA to 10mA) from an internal current source limiting the rate of change of the high impedance node. Typically an external resistor to GND is sufficient to set the slew rate at a desired level. Leaving the +SRC Pin open will give the highest speed performance. The external current ISTEAL for a resistor RSTEAL connected from +SRC to GND may be calculated by: ISTEAL = (VCC - 0.35)/RSTEAL. The Negative Slew Rate Control Pin adjusts the falling edge slew rate with an external current ISTEAL. ISTEAL supplies current (0mA to 10mA) to an internal current source limiting the amount of current being drawn from the circuit and thus limiting the rate of change of the high impedance node. Typically an external resistor to GND is sufficient to set the slew rate at a desired level. Leaving the -SRC Pin open will give the highest speed performance. The external current ISTEAL for a resistor RSTEAL connected from -SRC to GND may be calculated by: ISTEAL = (VEE + 0.35)/RSTEAL.
VEE1
VCC2
VEE2
VHIGH
VLOW
VOUT
DATA, DATA
HIZ, HIZ
+SRC
-SRC
90
HFA5253
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V Differential Input Voltage (DATA and HIZ) . . . . . . . . . . . . . . . . . . 5V Output Current Continuous (Note 1) . . . . . . . . . . . . . . . . . . . 160mA Input Voltage (Any pin except as specified) . . . . . . . . . . VCC to VEE VOUT Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to -4V VHIGH Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to -4V VLOW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to VEE VHIGH to VLOW Voltage. . . . . . . . . . . . . 11V to 0V (VHIGH > VLOW) Slew Rate Control Current (+SRC, -SRC) . . . . . . . . . . . . . . . . 12mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) 20 Ld PSOP Package . . . . . . . . . . . . . 49 2 (JC Measured At Copper Slug Top Center with Infinite Heat Sink) Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (PSOP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 50oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Internal Power Dissipation may limit Output Current below 160mA. 2. JA is measured with the component mounted on an evaluation PC board in free air. 3. Shorting the output to a voltage outside the specified range may damage the output.
Electrical Specifications
VCC = +11.2V; VEE = -6.4V; VIH = -0.9V; VIL = -1.75V; +SRC and -SRC are Not Connected, Unless Otherwise Specified (NOTE 4) TEST TEMP. LEVEL (oC) A A VHIGH = -3.25V to +8.5V VLOW = -3.5V to +8.25V A A A A VHIGH VLOW At 500mV At 250mV A A A B B VIH = 0V, VIL = -2V VIH = 0V, VIL = -2V VIH = 0V, VIL = -2V VIH = 0V, VIL = -2V VHIGH = -1V to 6.5V VLOW = -1.5V to 6V Fullscale = 5V, Note 6 Fullscale = 10.5V, Note 7 200mVP-P ISTEAL = 0mA to 10mA, 5V Step A A A A A A A A B B C C B B B 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25
PARAMETER INPUT CHARACTERISTICS (VHIGH, VLOW) VHIGH Input Offset Voltage VLOW Input Offset Voltage VHIGH Input Bias Current VLOW Input Bias Current VHIGH Voltage Range VLOW Voltage Range VHIGH to VLOW Differential Voltage Range VHIGH/VLOW Interaction (Notes 5, 17)
TEST CONDITIONS
MIN -150 -150 -50 -400 -3.5 -3.5 0 -3 0.4 -50 -700 -50 -400 0.95 0.95 -0.1 -0.8 1.0 1 -100 -120
TYP -50 -50 110 -110 2 20 110 -300 70 -80 0.97 0.97 100 VCC - 0.35 VEE + 0.35 -20
MAX UNITS +50 +50 400 50 8.5 8.5 9.5 4 40 8 5 700 50 400 50 1 1 0.1 0.8 2.8 2 100 80 mV mV A A V V V mV mV V V A A A A V/V V/V % % MHz V/ns V V ns ps ps
LOGIC INPUT CHARACTERISTICS (DATA, DATA, HIZ, HIZ) Logic Input Voltage Range Logic Differential Input Voltage DATA/DATA Logic Input High Current DATA/DATA Logic Input Low Current HIZ/HIZ Logic Input High Current HIZ/HIZ Logic Input Low Current TRANSFER CHARACTERISTICS VHIGH Voltage Gain VLOW Voltage Gain VHIGH/VLOW Linearity Error VHIGH/VLOW -3dB Bandwidth Typical Slew Rate Control Range +SRC Pin Voltage -SRC Pin Voltage SWITCHING CHARACTERISTICS (ZLOAD = 16 inches of RG-58 Terminated with 50) Propagation Delay (Notes 8, 10) Propagation Delay Match (Rising to Falling Edge, Notes 8, 10) Rising Edge Propagation Delay vs Duty Cycle (Notes 9, 10)
91
HFA5253
Electrical Specifications
VCC = +11.2V; VEE = -6.4V; VIH = -0.9V; VIL = -1.75V; +SRC and -SRC are Not Connected, Unless Otherwise Specified (Continued) (NOTE 4) TEST TEMP. LEVEL (oC) B B B 1VP-P, 20% - 80% (Note 11) 3VP-P, 10% - 90% (Note 11) 5VP-P, 10% - 90% (Note 12) Rise/Fall Time Match (Note 12) Minimum Output Pulse Width (Note 13) 1VP-P 3VP-P 5VP-P Overshoot/Undershoot/Preshoot Data Settling Time (Note 14) OUTPUT CHARACTERISTICS Output Voltage Swing Output Amplitude Voltage DC Output Resistance (Note 15) Output Leakage - HIZ Output Capacitance - HIZ Output Current - Active Output Short Circuit Range (Note 3) POWER SUPPLY CHARACTERISTICS (VHIGH = 5V Active, No Load) VHIGH Power Supply Rejection Ratio (Note 16) VLOW Power Supply Rejection Ratio (Note 16) Total Supply Current ICC1/IEE1 Supply Current ICC2/IEE2 Supply Current Supply Voltage Range VCC VEE VCC - VEE Power Dissipation NOTES: 4. Test Level: A = 100% production tested, B = Typical or limit based on lab characterization of a limited number of lots, C = Design Information, goal or condition. 5. VHIGH to VLOW Interaction is measured as the change in VOUT (the active channel) due to a change in the inactive channel. VHIGH Interaction at 250mV is measured as the deviation from 1V as VLOW is changed from 0V to 750mV (Referred to VOUT). VLOW Interaction at 250mV is measured as the deviation from 0V as VHIGH is changed from 1V to 250mV (Referred to VOUT). 6. For VHIGH = 0V to 5V, for VLOW = 0V to 5V, Fullscale = 5V, 0.1% = 5mV. Output Amplitude (VHIGH - VLOW) = 1VP-P . 7. For VHIGH = -2.5V to 8V, for VLOW = -3.0V to 7.5V, Fullscale = 10.5V, 0.1% = 10.5mV. Output Amplitude (VHIGH - VLOW) = 1VP-P. 8. 3V Step, 50% duty cycle, 200ns period. 9. 0V to 3V Step, 200ns period, Pulse Width is varied from 5ns to 195ns. 10. Test is performed into a 50 load with a 3V step. Measurement is made from the 50% of the input to 50% of output. 11. Limit based on calculation. 12. 5V Step, 50% duty cycle, 100ns period. 13. Minimum Pulse Width is measured 50% to 50% of specified amplitude with pulse peak at 100% of amplitude. 14. 3V Step, measured from 50% of input to 1% of reference value at 50ns. 15. Dynamic Output Resistance will be higher (Typ 48.5) than DC Output Resistance. DC Output Resistance is measured at 0V with IOUT set from 0mA to 40mA. 16. VHIGH = 2.6V, VLOW = 2.3V, VCC = 10.2V to 11.2V, VEE = -5.4V to -6.4V. 17. Input voltages VHIGH and VLOW are corrected for Offset Voltage and Gain Error. VCC = 11.2V, VEE = -6.4V, No Load No Load at VCC = 11V, VEE = -6.2V VOH - VOL -3V to 8V -3V to 8V A A A A C A A A A A B B A A A A 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 -3 0.25 45 -100 80 -4.0 90 11.0 -6.6 17.2 47 5 100 14 14 96 74 22 11.2 -6.4 8 9.0 49 100 9.0 40 40 98 11.4 -6.2 18.0 1.72 V V nA pF mA V mV/V mV/V mA mA mA V V V W 3VP-P To 1% B B B B B B B B B 25 25 25 25 25 25 25 25 25 25 25 25
PARAMETER Falling Edge Propagation Delay vs Duty Cycle (Notes 9, 10) Active to HIZ Delay (Note 10) HIZ to Active Delay (Note 10)
TEST CONDITIONS
MIN -80 1.5 2.8 350 700 1.1 -
TYP 20 2.0 3.3 450 890 1.3 100 1.0 1.2 2.0 5 10
MAX UNITS 120 2.5 3.8 500 1000 1.7 ps ns ns ps ps ns ps ns ns ns % ns
TRANSIENT RESPONSE (ZLOAD = 16 inches of RG-58 Terminated with 5pF) Rise/Fall Time
92
HFA5253 Functional Block Diagram
The HFA5253 functional block diagram is shown in on the first page of this data sheet. The control inputs, DATA and DATA, determine the output level. If DATA is at logic "1" and DATA is at logic "0", the output level will be the same as VHIGH. If DATA is at logic "0" and DATA is at logic "1", the output will be the same as VLOW. The control inputs, HIZ and HIZ, cause the output to become either active or high-impedance. If HIZ is at logic "1" and HIZ is at logic "0", the output will be in high impedance mode. If HIZ is at logic "0" and HIZ is at logic "1", the output will be enabled. The output impedance in the enabled mode is trimmed to 50. stage and the collector-base capacitance of the output stage transistors connected to the node VSO. The Slew Rate Control Pins, +SRC and -SRC, allow the user to control the amount of current available in the VHIGH and VLOW switch, respectively and thus the slew rate of node VSO. The output stage consists of cascaded emitter followers constructed in a typical push-pull manner as shown in the Schematic Diagram. However, transdiodes are added to increase the voltage breakdown characteristics of the output during high impedance mode. HIZ and HIZ control the mode of the output stage. A trimmed, NiCr resistor is added to provide the 50 output impedance. Overall, a symmetry of device types and paths is constructed to improve slew and delay symmetry. Both the VHIGH to VOUT path and the VLOW to VOUT path contain three NPN and three PNP transistors operating at similar collector currents. Thus the transient response of VHIGH to VLOW and VLOW to VHIGH are kept symmetrical. Also, a trimmable current reference (not shown) allows the AC parameters to be adjusted to maintain unit to unit consistency.
Circuit Schematic
The Pin Driver circuit consists of a switch, an output buffer, and two differential control elements as shown in the circuit Schematic Diagram. A two stage approach, separating the switch from the output buffer, allows the speed and accuracy requirements of the switch to be de-coupled from the load driving capability of the buffer. The patented switch circuitry [3] uses cascaded emitter followers as input buffers and also to switch the input VHIGH and VLOW to node VSO. Dual differential pairs controlled by the data timing (DATA and DATA) direct current to select either the VHIGH or VLOW switch. Matching transistor types and transdiodes improve linearity and lowers the voltage offset and offset drift. Stacking two emitter-base junctions allows the VHIGH to VLOW range to be extended to two Emitter - Base breakdown voltages of the process. The speed of the pin driver is largely determined by the current flowing through the switch
Application Information
The HFA5253 is a pin driver designed for use in automatic test equipment (ATE) and high speed pulse generators. Pin drivers, especially those with very high-speed performance, have generally been implemented with discrete transistors (sometimes GaAs) on a circuit board or in a hybrid. Recent IC process improvements, specifically Harris' UHF1 process [2], have enabled the manufacturing of the 500MHz and 800MHz silicon monolithic pin drivers, HFA5250, HFA5251 and now the HFA5253.
Schematic Diagram
VCC1 VHIGH /VLOW CONTROL +SRC SWITCHING STAGE OUTPUT STAGE VCC2 HIZ CONTROL
HIZ
HIZ
DATA
DATA VLOW VHIGH VOUT
VSO
VEE1 -SRC VEE2
93
HFA5253
The ultra high speed performance of the HFA5253 is a result of UHF1 process leverages: low parasitic collector-tosubstrate capacitance of the bonded wafer, low collector-tobase parasitic capacitance of the self-aligned base/emitter technology and ultra high fT NPN (8GHz) and PNP (5.5GHz) poly-silicon transistors. Linearity Error is calculated for every data point in the range and the worst case value is recorded. VHIGH TO VLOW INTERACTION VHIGH to VLOW Interaction is the change in VOUT (the active channel) due to the inactive channel. VHIGH Interaction is measured as the change in VOH from 1V as VLOW is moved from 0V to 750mV (VLOW is corrected for gain and offset errors). VLOW Interaction is measured as the change in VOL from 0V as VHIGH is moved from 1V to 250mV (with VHIGH corrected for gain and offset errors). The minimum recommended difference between VHIGH and VLOW for the HFA5253 is 250mV.
Definition of Terms
VOH AND VOL Output High Voltage and Output Low Voltage. VOH is the voltage at VOUT when the HIZ input is low and the DATA input is high. VOL is the voltage at VOUT when HIZ is low and DATA is low. The VOH and VOL levels are set with the VHIGH and VLOW inputs respectively. OFFSET VOLTAGE Offset Voltage is the DC error between the voltage placed on VHIGH or VLOW and the resulting VOH and VOL. VHIGH Offset Voltage Error is obtained by measuring VOH with VHIGH set to 0V and VLOW set to -2.5V to minimize interaction effects. VLOW Offset Voltage Error is the measurement of VOL with VLOW set to 0V and VHIGH set to +7.5V. GAIN Gain is defined as the ratio of output voltage change to input voltage change for a defined range. VHIGH Gain is calculated with the following equation with VLOW fixed at -2.5V:
V OH ( V HIGH at 6.5V ) - V OH ( V HIGH at -1V ) V HIGH GAIN = ----------------------------------------------------------------------------------------------------------------7.5
Speed Advantage
Harris Pin Drivers on bonded-wafer technology definitely have a speed advantage, coming from the low collector-tosubstrate capacitance and the high fT of the transistors. In addition, the patented switching stage which fits uniquely to Harris' UHF1 process is another big contributor for the high speed. This switching circuitry requires low series-resistance NPN and PNP transdiodes available in UHF1. The rise and fall times of the pin driver are largely determined by the slew rate at the node VSO in the Schematic. The dominant mechanism for the slew rate is the charging/discharging of the collector-base capacitors of the transistors connected to the node VSO. The charging/discharging currents are coming from the switching stage current sources. The fast rise and fall times are achieved because of the negligible collector-tosubstrate capacitance and the small base-collector capacitance due to the self-aligned recessed oxide [2]. The DATA/DATA differential stage is not a factor for the speed if its current sources have enough current not to bottleneck the transient. However it should be noted that the propagation delay mismatch is determined by this stage. Sufficient current is allocated to the differential stage current sources to best match the low-to-high and high-to-low transient propagation delays. The specified load condition is a 16 inch 50 SMA cable with a 5pF capacitor at the end of the cable. This load simulates a typical ATE environment for a DUT (Device Under Test) with high impedance (>1k) digital inputs. The rise/fall time for HFA5253 with 5VP-P is typically 1.3ns. Pin drivers, built out of the same circuit structure as shown in the Schematic, can be made faster by trimming for a higher power supply current. Currently the pin driver has rise/fall times of less than 1ns (10% to 90% of 5VP-P) when ICC is trimmed to 125mA. Further speed enhancement will be made if there is a market demand.
VLOW Gain is calculated in a similar manner:
V OL ( V LOW at 6V ) - V OL ( V LOW at -1.5V ) V LOW GAIN = ------------------------------------------------------------------------------------------------------------7.5
VHIGH is held fixed at 7.5V. These Gain calculations minimize the effects of Interaction and End Point Nonlinearities. LINEARITY ERROR Linearity Error is a measure of output voltage worst case deviation from a straight line that has been corrected for offset and 7.5V Gain. Linearity Error is given as a percentage of fullscale and is done in two ranges, 5V and 10.5V. DATA is measure at 0.5V steps from -2.5V to 8V for VHIGH and -3V to 7.5V for VLOW. The Linearity Error equation is as follows for 10.5V fullscale:
V OUT ( IDEAL ) = V IN x Gain + Offset V OUT - V OUT ( IDEAL ) Linearity Error = ------------------------------------------------------------10.5
Basic ATE System Application
Figure 1 shows a pin driver in a typical per-pin ATE system. The pin driver works closely with the Dual-Level Comparator and the Active Load. When the DUT pin acts as an input waiting for a series of digital signals, the pin driver becomes active with a logic "0" applied on the HIZ pin and provides the DUT pin with digital signals. When the DUT pin acts as an output, the pin driver output will be in high impedance mode (HIZ) with a logic
The Linearity Error equation is as follows for 5V fullscale:
V OUT - V OUT ( IDEAL ) Linearity Error = ------------------------------------------------------------5
94
HFA5253
"1" applied to the "HIZ" pin. During this high impedance mode the pin driver presents a capacitance of less than 5pF to the DUT. Special care has to be taken to match the impedance (to 50) at the pin driver output to minimize reflections. The Dual-Level Comparator detects the logic levels of the DUT pin when it acts as an output. The comparator has two threshold level inputs, VCH and VCL. The logic level information of the DUT pin output is sent to the edge/window comparator through the Dual-Level Comparator. The edge/window comparator interprets this information in terms of corresponding transient performance in conjunction with the timing information. Thus it detects any possible failure transients. The formatter sends a sequence of digital information to the pin driver which contains logic information over time. The Active Load is enabled when the DUT pin acts as an output. It simulates the load of the DUT pin by sinking or sourcing programmed current. Finally the sequencer controls the overall activities of the automatic testing. connected to each of the pins, DATA and HIZ through a 50 chip resistor to monitor the pulse signals.
PARTS LIST QTY 6 4 2 8 2 7 1 4 4 2 VALUE 470pF 0.1F 10F 50 100 SMA Jacks 20 Lead PSOP 4-40 4-40 COMPONENT Chip Cap: 0805 Chip Cap: 0805 Tant. Chip Res: 0805 Chip Res: 0805 Wide Body HFA5253 1" Standoff 1/4" Screws
Twisted Wire Assemblies with 4 Wires Each: One for VCC , VHIGH , +SRC, GND; and 1 for VEE , VLOW, -SRC, GND.
Decoupling Circuit for Oscillation-Free Operation
To ensure oscillation-free operation in ATE or pulse generator applications, the pin driver needs an appropriate decoupling circuit on a printed circuit board which consists of chip capacitors and chip resistors. Figures 2, 3, and 4 refer to a proven decoupling circuit currently working in the lab and a 1X scale film of its associated PC board (metal level). Do not connect the VCC1 and VCC2 pins or the VEE1 and VEE2 pins together immediately, rather run separate traces until they can be joined at a large bypass capacitor (0.1F || 10.0F). The control pins, DATA, DATA, HIZ, and HIZ are fed ECL signals through 50 micro-strip lines terminated with 50 for impedance matching since the input impedance at these pins is much higher than 50. At the end of the micro-strip lines there is usually a high-speed pulse generator with an output impedance of 50. A 50 micro-strip line is
The input pins, VHIGH , VLOW, +SRC, and -SRC need to be protected from any capacitively coupled AC noise. Normally this protection can be achieved by having a low pass filter consisting of a 50 chip resistor and a chip capacitor, 470pF for VHIGH/VLOW and 0.1F for +SRC/-SRC. Without this protection circuit the pin driver may oscillate due to signals fed back from the output through the PC board ground. The power supply pins, VCC1, VCC2 , VEE1, and VEE2 , require decoupling chip capacitors of 470pF, 0.1F, 10F. Having decoupling capacitors close to VCC2 and VEE2 is essential since large AC current will flow through either VCC2 or VEE2 during transients. The output of the pin driver is usually connected to the deviceunder-test (DUT) through 50 micro-strip line and coaxial cable which carries the signal to a high input impedance DUT pin.
CLOCK, START
TIMING
HIZ
ACTIVE LOAD 50 DUT
DATA MEMORY FORMATTER DATA PIN DRIVER
DATA MEMORY SEQUENCER FAIL
EDGE/ WINDOW COMPARATOR
VCH VCL DUAL LEVEL COMPARATOR
FAIL MEMORY
TIMING
FIGURE 1. TYPICAL ATE SYSTEM
95
HFA5253
(+11.2V) VCC GND VHIGH +SRC
+ 10F
0.1F
470pF 50 1 20 19 18 17 HFA5253 16 15 14 13 12 11 50
0.1F
D-SCOPE
470pF 470pF
50 50 100 DATA DATA
2 3 4 5
VOUT
6 7
50
50
HIZ
470pF 470pF
8 9 10
50 0.1F
100
HIZ 50
10F +
0.1F
470pF
HIZ-SCOPE
(-6.4V) VEE
GND
VLOW
-SRC
FIGURE 2. DECOUPLING CIRCUIT SCHEMATIC
HFA5253 EVAL BOARD HARRIS SEMICONDUCTOR D-SCOPE GND DATA
470pF 100 50 470pF 50 470pF 0.1 10
VH +SRC
DATA
VCC VOUT
50 50 50 50 10
470pF 50 100 50 470pF 470pF
VEE -SRC VL
HIZ
0.1
HIZ HIZ-SCOPE
GND
FIGURE 3. 1X PC BOARD LAYOUT (BOTTOM VIEW)
FIGURE 4. 1X PC BOARD LAYOUT (TOP VIEW)
References
[1] Taewon Jung and Donald K. Whitney Jr., "A 500MHz ATE Pin Driver," Bipolar Circuits and Technology Meeting Proceedings, pp238-241, October 1992. [2] Chris K. Davis et. al., "UHF1: A High Speed Complementary Bipolar Analog Process on SOI," Bipolar Circuits and Technology Meeting Proceedings, pp260-263, October 1992. [3] Donald K. Whitney Jr., "Symmetrical, High Speed, Voltage Switching Circuit," United States Patent Pending, Filed November 1991.
96
HFA5253 Typical Performance Curves
6
4
VOUT (V)
ISTEAL = 0mA 2
ISTEAL = 10mA
ISTEAL = 5mA 0
ISTEAL = CURRENT FLOWING OUT OF +SRC FOR RISING EDGE OR -SRC FOR FALLING EDGE -2 0 2 4 6 8 10 TIME (ns) 12 14 16 18 20
FIGURE 5. 5V STEP RESPONSE vs SLEW RATE CONTROL
6
ISTEAL= -10mA 4
VOUT (V)
2 ISTEAL= -5mA
ISTEAL= 0mA 0
-2 0 2 4 6 8 10 TIME (ns)
ISTEAL = CURRENT FLOWING OUT OF +SRC FOR RISING EDGE OR -SRC FOR FALLING EDGE 12 14 16 18 20
FIGURE 6. 5V STEP RESPONSE vs SLEW RATE CONTROL
97
HFA5253 Typical Performance Curves
(Continued)
3
2
OUTPUT (V)
1
0
1.087ns
0
2.5 TIME (ns)
5
FIGURE 7. MINIMUM PULSE WIDTH, 1V/DIV.; 500ps/DIV.
0.05
0
-0.05 VOUT - VIN (V)
-0.1 VHIGH
-0.15 VLOW
-0.2
-0.25 -4 -2 0 2 VIN (V) 4 6 8 10
FIGURE 8. VOUT ERROR vs VIN
98
HFA5253 Typical Performance Curves
0.2 0.02 TYPICAL 5 UNITS 0.15
(Continued)
0.015
LINEARITY (% OF 10.5V FULLSCALE)
0.1
0.01 LINEARITY (V) LINEARITY (V)
0.05
0.005
0
0.0
-0.05
-0.005
-0.1 -4 -2 0 2 VIN (V) 4 6 8 10
-0.01
FIGURE 9. VHIGH LINEARITY ERROR 10.5V FULLSCALE
0.25
TYPICAL 5 UNITS 0.2 0.02 LINEARITY (% OF 10.5V FULLSCALE)
0.15
0.1
0.01
0.05
0
0.0
-0.05 -4 -2 0 2 VIN (V) 4 6 8
FIGURE 10. VLOW LINEARITY ERROR 10.5V FULLSCALE
99
HFA5253 Typical Performance Curves
1.06 VHIGH ACTIVE (NOMINAL 1.0V) 1.05 MINIMUM RECOMMENDED VHIGH TO VLOW VOLTAGE
(Continued)
1.04
1.03 VOUT (V)
1.02
1.01
1
0.99
0.98 0 0.1 0.2 0.3 0.4 0.5 VLOW INPUT (V) 0.6 0.7 0.8 0.9 1
FIGURE 11. VHIGH/VLOW INTERACTION
0.01 VLOW ACTIVE (NOMINAL 0.0V)
0
-0.01 VOUT (V) -0.02 -0.03 MINIMUM RECOMMENDED VHIGH TO VLOW VOLTAGE -0.04 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 VHIGH INPUT (V)
FIGURE 12. VHIGH/VLOW INTERACTION
100
HFA5253 Typical Performance Curves
30 75oC
(Continued)
20
50oC
10 25oC OUTPUT LEAKAGE (nA) 0
-10 25oC -20
-30 50oC -40 75oC -50
-60 -4 -2 0 2 4 6 8 10 OUTPUT VOLTAGE (V)
FIGURE 13. HIZ OUTPUT LEAKAGE
3.5 TYPICAL 6 UNITS 3
2.5
+SLEW RATE (V/ns)
2
1.5
1
0.5 NOTE: SLEW RATE WILL CONTINUE TO DECLINE AS +SRC CURRENT IS INCREASED BEYOND 12mA 0 0 1 2 3 4 5 6 7 8 9 10 11 12 +SRC CURRENT (mA)
FIGURE 14. (+) SLEW RATE vs ISTEAL
101
HFA5253 Typical Performance Curves
3.5 TYPICAL 6 UNITS 3
(Continued)
2.5
-SLEW RATE (V/ns)
2
1.5
1
0.5 NOTE: SLEW RATE WILL CONTINUE TO DECLINE AS -SRC CURRENT IS INCREASED BEYOND 12mA 0 -15 -10 -SRC CURRENT (mA) -5 0
FIGURE 15. (-) SLEW RATE vs ISTEAL
3.5 VHIGH = 8V, ISTEAL = 0mA 3 AVERAGE OF 8 UNITS
2.5 VLOW = 0V, ISTEAL = 0mA +SLEW RATE (V/ns) VLOW = -3V, ISTEAL = 0mA 2
1.5 VHIGH = 8V, ISTEAL = 10mA 1 VLOW = 0V, ISTEAL = 10mA 0.5 VLOW = -3V, ISTEAL = 10mA 0 0 1 2 3 4 5 6 VOLTAGE STEP (VHIGH - VLOW) (V) 7 8 9 10
NOTE: The family of curves shows slew rate as a function of common mode voltage. A voltage is provided for each trace specifying one level of the voltage step for which slew rate is measured. Example 1: Top Trace (VHIGH = 8V, ISTEAL = 0mA). A voltage step of 1V goes from VLOW = 7V to VHIGH = 8V and a voltage step of 9V goes from VLOW = -1V to VHIGH = 8V. Example 2: Trace (VLOW = -3V, ISTEAL = 0mA). A voltage step of 1V goes from VLOW = -3V to VHIGH = -2V and a voltage step of 9V goes from VLOW = -3V to VHIGH = 6V. FIGURE 16. (+) SLEW RATE vs AMPLITUDE
102
HFA5253 Typical Performance Curves
4 VHIGH = 8V, ISTEAL = 0mA 3.5 VLOW = 0V, ISTEAL = 0mA 3 VLOW = -3V, ISTEAL = 0mA -SLEW RATE (V/ns) 2.5 AVERAGE OF 8 UNITS
(Continued)
2
1.5 VHIGH = 8V, ISTEAL = 10mA VLOW = 0V, ISTEAL = 10mA 1 VLOW = -3V, ISTEAL = 10mA
0.5 0 1 2 3 4 5 6 VOLTAGE STEP (VHIGH -VLOW) (V) 7 8 9 10
NOTE: The family of curves shows slew rate as a function of common mode voltage. A voltage is provided for each trace specifying one level of the voltage step for which slew rate is measured. Example 1: Top Trace (VHIGH = 8V, ISTEAL = 0mA). A voltage step of 1V goes from VHIGH = 8V to VLOW = 7V and a voltage step of 9V goes from VHIGH = 8V to VLOW = -1V. Example 2: Trace (VLOW = -3V, ISTEAL = 0mA). A voltage step of 1V goes from VHIGH = -2V to VLOW = -3V and a voltage step of 9V goes from VHIGH = 6V to VLOW = -3V. FIGURE 17. (-) SLEW RATE vs AMPLITUDE
CLOAD = 6.5pF 0.6
0.4 VOUT (V) CLOAD = 4pF CLOAD = 10.2pF
0.2
0 ZLOAD = 1k || CLOAD 0 1 2 3 4 5 TIME (ns) 6 7 8 9 10
FIGURE 18. 0.5V STEP RESPONSE vs CLOAD
103
HFA5253 Typical Performance Curves
0.6
(Continued)
0.4
VOUT (V)
0.2 CLOAD = 10.2pF
CLOAD = 4pF 0 CLOAD = 6.5pF ZLOAD = 1k || CLOAD -0.2 0 1 2 3 4 5 TIME (ns) 6 7 8 9 10
FIGURE 19. 0.5V STEP RESPONSE vs CLOAD
104
HFA5253 Die Characteristics
DIE DIMENSIONS: 2670m x 1730m x 525m METALLIZATION: Type: Metal 1: Cu (2%) SiAl/TiW Thickness: Metal 1: 8kA 0.4kA Backside: Gold Type: Metal 2: Cu (2%) Al Thickness: Metal 2: 16kA 0.8kA PASSIVATION: Nitride, 4kA 0.5kA TRANSISTOR COUNT: 113 SUBSTRATE POTENTIAL: Floating
Metallization Mask Layout
HFA5253
+SRC VHIGH VCC1
DATA VCC2 DATA
VOUT
HIZ VEE2 HIZ
-SRC
VLOW
VEE1
105
HFA5253 Power Small Outline Plastic Packages (PSOP)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M20.3A
20 LEAD POWER SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 8.25 7.40 4.44 MAX 2.65 0.30 0.51 0.32 13.00 8.63 7.60 4.82 NOTES 9 3 10 4 10 5 6 7 8o Rev. 0 6/95
MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.325 0.2914 0.175
MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.340 0.2992 0.190
A1 B C D

A1 0.10(0.004) C
D1 E E1 e H h
e
B 0.25(0.010) M C AM BS
0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27
TOP VIEW N
L N
E1 D1 1 2 3
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Exposed copper heat slug flush with top surface of package. All other dimensions conform to JEDEC MS-013AC Issue C. 11. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
POWER SOP PACKAGE (HEAT SLUG SURFACE IS ELECTRICALLY FLOATING)
106

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